The present disclosure relates generally to semiconductor devices and more particularly, to the improved semiconductor devices with reduced impact from alien particles.
Semiconductor devices are unavoidably impacted by alien energy particles existing in the universe. For example, the cosmic ray contains high-energy neutrons, which may strike some isotopes in the device package and semiconductor device to release alpha particles. These energized particles will impact the performance of semiconductor devices.
For example, taking semiconductor memories, they are comprised of large arrays of individual memory cells. Each memory cell stores a “0” or a “1” data bit as an electrical low or high voltage state. At least 8 data bits may compose a data byte. At least 16 data bits may compose a data word. In each memory operation cycle, at least one byte is typically written into, or read from the memory array. Cells are physically arranged as vertical data (bit lines) and the horizontal word lines to facilitate the reading and writing of the data within the memory array. A data read or write cycle occurs when word lines, as well as a pair of bit lines, are activated. The cell accessed at the intersection of the word lines and the bit lines will either receive written data from the bit lines or will deliver written data to the bit lines. Cells can typically be accessed in a random order.
A cell is composed of an electronic circuit, typically comprised of multiple transistors. A Static Random Access Memory (SRAM) cell is most typically composed of a plurality of metal-oxide-semiconductor field-effect-transistors (MOSFETs). The most common type of SRAM is composed of six-transistor (6T) cells, each of which includes two P-type MOSFETs (PMOSFETs) and four N-type MOSFETs (NMOSFETs). A cell is arranged with two inverters that are accessed from two complementary bit lines through two access transistors that are controlled by a word line. This structure features low power consumption and good immunity to electronic noise on the bit and word lines, and to charges introduced by alpha particles.
However, as more technologies that utilize semiconductor memories requiring a smaller footprint and a higher mobility, physical space savings in semiconductor memory designs become increasingly important. In particular, in order to continually achieve size and performance advantages, cell geometries must continually shrink. However, as cell geometries shrink, one problem arises. Each of the two inverters storage nodes in an SRAM cell is composed of the capacitances of the gates of the two transistors of that inverter. As geometries shrink, the storage capacitances also shrink. The charge, which is stored as data, is now so small that its data integrity is now extremely susceptible to disturbance from electrical noise on either of the bit lines, the word line, and to charges introduced by the arrival of an alpha particle. Alien alpha particles are charged ions produced within the packaging material surrounding the semiconductor memory and/or the semiconductor material when high-energy cosmic rays (neutrons) strike certain isotopes of the said material. The alpha particles may then become electrical noise to disturb the data integrity of the local memory cells. The frequency of this disturbance error caused by this electrical noise, in the form of alpha particles, is known as soft error rate. As soft error rate increases, the risk of catastrophic data integrity loss increases. Noise immunity, therefore, is an area in semiconductor memory designs that merits increasing concern.
Desirable in the art of semiconductor device designs are an additional design that increases noise immunity, thereby reducing impacts caused by alien particles.